Development board based on CPU Zilog Z80 and MCU Zilog Z8
Why?
The main reason why I started to work on this project was curly developed topic
"NEW MODEL OF SPECTRUM" (link is accesible for registered and logged-in users only) in
Speccy newsgroup on server Pandora.cz. (available in Czech and Slovak language only)
With power of old-good and by-decades-verified Zilog Z80CPU and new positive and powerful features of Zilog Z8Encore! we can build a nice synergy platform powered by rich set of features.
And last but not least is the compatibility (not perfect yet) with legendary ZX Spectrum.
Architecture
Function blocks of development board are described on following block diagram:
For better clarity I intentionally cut out following peripherals from block diagram:
external I2C EEPROM
graphics display 84*48 pixels driven by SPI (from cellular phone Nokia 3310)
serial port module (with MAX232)
DBG interface Z8Encore!
The heart of development board is the Z8Encore! MCU, which drives all other components of the board.
After self-initialization and default port setup (I2C, LCD, SRAM) it does the following tasks:
brings Z80CPU to the RESET state - all 3-state buses to high-impedance state
fills very first 16kB of SRAM with Z80CPU code (now it's ROM of the ZX Spectrum 48K)
initializes it's internal Timer0 in role of interrupt generator (/INT) for Z80CPU (signal trace compatible with ZX Spectrum ULA)
releases SRAM control signals
returns bus control to Z80CPU
finishes reset of Z80CPU (signal /RESET of Z80CPU do logic HIGH)
Z8Encore! drives these bus signals of Z80CPU:
/RESET (logic LOW during initialization)
/INT (50/sec, 9ms in LOW)
/BUSRQ (requires Z80CPU to release the bus, after that Z8 can access SRAM)
Z8Encore! also allows/denies Z80CPU to access SRAM (signals /CS a /WR).
In role of display device I utilized graphics LCD with resolution 84*48 pixels (around one third of horizontal resolution and quarter of vertical resolution of ZX Spectrum screen).
After first initialization, Z8Encore! periodically refreshes information on LCD. While Z8 wants to read data from SRAM, it activates /BUSREQ signal of Z80CPU. After this request Z80CPU releases the bus and allow DMA controller (Z8 in this design) to access memory directly.
Z8 displays a copy of video RAM on LCD (last 6 lines).
Schematics
There is MAX232 connected to Z8 UART0 missing in current version of schematics.
I used these development tools during prototyping dual-Zilog board:
Zilog Developer Studio II (SW for Windows) - Z8Encore! code development
Smart Cable - Z8Encore! programming device
Ic-prog - excellent SW for Windows which can program wide spectrum of IC
Development programmer AN589 - for ISP-programmable PIC MCUs (I used it for EEPROM programming)
Expected improvements
MMC card will be attached to Z8 SPI interface to provide storage solution for Z80CPU software
Z8F6401 lacks I/Os and should be replaced to other type of Z8Encore! MCU with more pins (e.g. Z8F6423). This config allows direct memory address generation and avoid shift registers.
Allow Z80CPU to be able to access Z8Encore! peripherals (UART, IrDA, I2C, SPI, timers etc.). Z8 acts as intelligent I/O controller for Z80CPU
Memory paging (ZX Spectrum 128k, CP/M or -at least- utilization of full capacity of SRAM chip - 512kB)
Other type of display controller (display full ZX Screen)
Keyboard support (matrix or PS/2)
Comments and suggestions
Design of this development board is not finished yet. I hope I will be able to finish my work in next few months.
If you have any questions, suggestions or comments, please send them to
my e-mail.
